Huawei Releases Revised Tau Theory Paper with Mass-Produced Chip Test Data, Unveils AI Hardware Roadmap
He Tingbo, head of Huawei’s semiconductor division, has published the revised V2 paper titled A time scaling theory for multi-layer electronic systems, widely known as the Tau (τ) Theory, on ChinaXiv, a preprint platform operated by the Chinese Academy of Sciences. The updated version was released roughly forty days after the initial V1 publication, marking a full shift from theoretical framework to verified engineering evidence. As of publication cut-off, the paper has recorded more than 288,000 page views and over 60,000 full-text downloads.
The most substantial advancement introduced in the V2 manuscript is the public disclosure of complete test metrics collected from mass-produced silicon wafers. Previous interviews confirm the hardware developed under this theoretical framework delivers leap-forward performance improvements compared with chips rolled out in 2025. Both Kirin 2026 and Kirin 2027 have finished tape-out procedures. New consumer devices powered by Kirin 2026 will enter commercial availability this autumn.
The Tau Theory sets out clear performance growth trajectories for artificial intelligence hardware infrastructure. Modelling contained within the paper forecasts a more than 100-fold rise in overall integration density for AI hardware systems by 2035. Huawei’s Ascend AI accelerator series will continue leveraging mature Chiplet and 2.5D packaging architectures for Ascend 910C launched in 2025 and Ascend 950 due for release in 2026, alongside the follow-up Ascend 990 product line. Logic folding technology will be integrated into AI accelerator products from around 2030 onwards to drive density and efficiency gains.
The paper outlines a coherent ten-year technical evolution blueprint, yet highlights multiple industry-wide collaborative tasks spanning electronic design automation toolchains, unified industrial benchmarks, device physics research and sustainable commercial operating frameworks. Joint cross-industry research and standardisation work will advance each segment of the semiconductor value chain.
The 2026 World Artificial Intelligence Conference (WAIC 2026) will run from 17 to 20 July across exhibition venues in Shanghai. The Atlas 950 SuperPoD, the largest-scale supernode computing hardware available on the market, will make its physical debut at the event. The supernode platform supports a maximum expansion to 8,192 NPU cards, engineered to deliver high-throughput training and low-latency inference for trillion-parameter large language models, with leading specifications in total computing power, shared memory pool and interconnection bandwidth relative to competing overseas supernode solutions.
The verified mass-production data laid out in the second iteration of the Tau Theory paper, paired with the physical showcase of the Atlas 950 SuperPoD, demonstrates Huawei’s expanding pipeline of end-to-end semiconductor and AI computing hardware solutions. Cross-functional R&D teams continue refining logic folding implementation, packaging processes and supernode interconnection architectures to align mobile system-on-chip and data centre accelerator development timelines.
